Electrostatic discharge (ESD) refers to the phenomenon whereby an electrical current of high magnitude and short duration is discharged at the package terminals of an integrated circuit due to static charge build-up on the integrated circuit (IC) package or on a nearby object, such as a human being or an IC handling machine. Without ESD protection circuitry, an ESD event can damage the IC. Accordingly, circuit designers have developed ESD protection circuitry to discharge ESD currents in a short time in a nondestructive manner
A diode string represents one type of ESD circuit that can be used to discharge ESD currents. The diode string is formed in bulk material of a semiconductor substrate by series-connected P-N junctions typically formed in nwell regions. In particular, each n-well formed in the P-type bulk material is tapped via an n+ diffusion and is connected to the p+ junction of the next diode. The combination of a P+ diffusion contained in an nwell over a P-type substrate forms a parasitic PNP transistor by default, such that the “diode string” is really a chain of PNP transistors. Within the diode string, each PNP transistor has a vertical current gain (β), which effects the diode string operation, including the total substrate current, the effective on resistance (RON), and so on.
As the process technologies advance and the semiconductor technology scales, the vertical current gain (β) also tends to get smaller due to the n-well retrograde doping profile, in order to fight latch-up. Unfortunately, as the vertical current gain (β) decreases, the on-resistance (RON) of the diode string increases, which can adversely impact the performance of the diode string in response to an ESD event by reducing the amount of current shunted to the substrate. In general, shunting current to the substrate provides an extra current path which contributes to lowering the effective resistance otherwise exhibited by the series connection of diodes.
One type of ESD protection circuit includes interconnections between diode strings of adjacent input/output (I/O) pads to implement distributed diode strings. This configuration is described in United States Patent Application Publication 2014/0035091, which is incorporated herein by reference in its entirety for all purposes. Distributing the ESD event through multiple, smaller parallel diode strings makes it possible to use tapered diode strings to reduce the cell height of the diode strings without reducing ESD protection.